This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-078882, filed Mar. 21, 2000; and No. 2000-229158, filed Jul. 28, 2000, the entire contents of both of which are incorporated herein by reference.
The present invention relates to a gate driver for making control so as to turn ON/OFF an output element such as a power MOSFET, an IGBT (Insulated Gate Bipolar Transistor), or the like, and a power converter in which the gate driver and the output element are integrated in one-chip.
FIG. 1 is a block diagram showing the schematic structure of a conventional gate driver and a power converter. This circuit is constructed by an edge detection circuit 1, an ON pulse generation circuit 2, an OFF pulse generation circuit 3, a status hold circuit 4, an output element 9, and the like. The part surrounded by a broken line corresponds to the gate driver 10. The power converter is constructed by the gate driver 10 and the output element 9.
The edge detection circuit 1 is inputted with a control input signal and a protect operation signal and detects rise and fall of the control input signal. The ON pulse generation circuit 2 generates an ON pulse Pon in response to a leading edge of the control input signal detected by the edge detection circuit 1, and the OFF pulse generation circuit 3 generates an OFF pulse Poff in response to the trailing edge of the input signal detected by the edge pulse detection circuit 1. The status hold circuit 4 is inputted with an ON pulse Pon outputted from the ON pulse generation circuit 2, and a OFF pulse Poff outputted from the OFF pulse generation circuit. Based on the ON pulse Pon and OFF pulse Poff, the gate driving status of the output element 9 is held. That is, the status hold circuit 4 drives the gate of the output element 9 to turn on and maintains it turned on until the OFF pulse Poff is inputted.
When a leading edge is detected (timing t1) as shown in FIG. 2 in the structure as described above, an ON pulse Pon is outputted from an ON pulse generation circuit 2 and the gate of the output element 9 is driven to turn on. This ON status is held by the status hold circuit 4. When a trailing edge of the control input signal is detected by the edge detection circuit 1 (timing t2), an OFF pulse Poff is outputted from the OFF pulse generation circuit 3, and driving of the gate of the output element is stopped and turned off. This off status is held by the status hold circuit 4.
Meanwhile, when the protect operation signal rises in a state where a leading edge of the control input signal is detected by the edge detection circuit 1 and the gate of the output element is driven to turn on, the control input signal falls inside the edge detection circuit 1. This fall is detected and an OFF pulse Poff is outputted from the OFF pulse generation circuit 3 (timing t4), and driving of the output element 9 is stopped to turn off.
However, no OFF pulse Poff is generated even when an operation error which causes the output element 9 to turn on occurs (timing t5) due to some reason (noise, a voltage shift of an output part, or the like) and the operation error causes a protect operation signal to rise, in a state in which the control input signal indicates OFF (xe2x80x9cLxe2x80x9d level) of the output element 9. This is because the structure is arranged such that the control input signal is fixed to the xe2x80x9cLxe2x80x9d level inside the edge detection circuit 1 in synchronization with the protect operation signal. Therefore, at the timing t6, the control input signal is at xe2x80x9cLxe2x80x9d level and no trailing edge exists. Consequently, no OFF pulse Poff is generated. As a result, it is not possible to eliminate an abnormal operation which causes the output element 9 to turn on although the output element 9 should originally be turned off, but the output element 9 holds the on status, leading to breakdown.
FIG. 3 is a circuit diagram showing another structural example of a conventional gate driver. This gate driver 100 controls output elements (switching elements which are IGBTs in this case) 6 and 8 having a push/pull structure, and comprises a high-side gate driver circuit 101 for controlling a high-side switching element 6 to turn ON/OFF, a low-side gate driver circuit 102 for controlling the low-side switching element 8 to turn ON/OFF. The high-side gate driver circuit 101 is constructed by an edge detection circuit 1xe2x80x2, an ON pulse generation circuit 2, an OFF pulse generation circuit 3, a latch circuit (corresponding to the status hold circuit 4 in FIG. 1) 4xe2x80x2, a drive circuit 5, and the like. The low-side gate driver circuit 102 is structured to include a drive circuit 7.
The gate driver 100 drives the switching elements 6 and 8 in the high and low sides at individual operation voltages, respectively, so that the circuit in the high-side system and the circuit in the low-side system are operated at different reference voltages, respectively. The edge detection circuit 1xe2x80x2, ON pulse generation circuit 2, and OFF pulse generation circuit 3 in the high-side gate driver circuit 101 are created by circuits of the low-side system, and the latch circuit 4xe2x80x2 and drive circuit 5 are created by circuits of the high-side system. Also, the drive circuit 7 is created by a circuit of the low-side system. Further, the high-side input signal HS and the low-side input signal LS are both inputted as signals based on a reference voltage of the low-side system.
The high-side input signal HS for control the high-side switching element 6 to turn ON/OFF is inputted to the edge detection circuit 1xe2x80x2, and the detection output from this edge detection circuit 1xe2x80x2 is supplied to the ON pulse generation circuit 2 and the OFF pulse generation circuit 3. The ON pulse generation circuit 2 generates an ON pulse Pon in response to the leading edge of the high-side input signal HS detected by the edge detection circuit 1xe2x80x2. Also, the OFF pulse generation circuit 3 generates an OFF pulse Poff in response to the trailing edge of the high-side input signal HS detected by the edge detection circuit 1xe2x80x2. The ON pulse Pon outputted from the ON pulse generation circuit 2 and the OFF pulse Poff outputted from the OFF pulse generation circuit 3 are supplied to the latch circuit 4xe2x80x2 so that ON/OFF information of the high-side switching element is held. Further, a high-side gate signal HG is outputted from the drive circuit 5, based on the latch circuit 4xe2x80x2, and is supplied to the gate of the high-side switching element 6, so that this high-side switching element 6 is driven.
Meanwhile, the low-side input signal LS for controlling the low-side switching element 8 to turn ON/OFF is supplied to the drive circuit 7. The low-side gate signal LG outputted from this drive circuit 7 is supplied to the gate of the low-side switching element 8, so that this low-side switching element 8 is driven.
The high-side switching element 6 and the low-side switching element 6 are constructed in a push/pull structure. The collector and emitter of the high-side switching element 6 are respectively connected to a power supply VC and an output terminal 11. The collector and emitter of the low-side switching element 8 are respectively connected to the output terminal 11 and a ground point GND.
Next, with respect to the structure as described above, operation will be explained with reference to a timing chart shown in FIG. 4. Driving of the high-side switching element 6 is carried out as follows. When a leading edge (timing t1) of the high-side input signal HS is detected by the edge detection circuit 1xe2x80x2, an ON pulse Pon is generated from the ON pulse generation circuit 2. When a trailing edge of the high-side input signal HS (timing t2) is detected, an OFF pulse Poff is generated from the OFF pulse generation circuit 3. Since a pulse is used as the high-side input signal HS, signals can be transmitted while reducing, as much as possible, the current generated by the difference between the operation voltages or reference potentials of the circuits of the high-side system and the low-side system.
The ON/OFF information of the high-side switching element 6 transmitted in form of a pulse depending on the high-side input signal HS is inputted to the latch circuit 4 and held therein. Further, based on the ON/OFF information held in this latch circuit 4xe2x80x2, the high-side gate signal HG is outputted from the drive circuit 5, thereby to drive the high-side switching element 6. That is, in response to the ON pulse Pon outputted from the ON pulse generation circuit 2, the high-side gate signal HG outputted from the drive circuit 5 goes to a high level (xe2x80x9cHxe2x80x9d level), so that the high-side switching element 6 is driven to turn on and this driving status is held by the latch circuit 4. Further, when an OFF pulse Poff is outputted from the OFF pulse generation circuit 3, the high-side gate signal HG outputted from the drive circuit 5 goes to a low level (xe2x80x9cLxe2x80x9d level), so that driving of the high-side switching element 6 is stopped (OFF).
In contrast, driving of the low-side switching element 8 is carried out in a manner that the low-side input signal LS is supplied to the drive circuit 7 and the low-side gate signal LG is supplied to the gate of the low-side switching element 8. That is, when the low-side input signal LS rises to the xe2x80x9cHxe2x80x9d level (timing t3), the low-side gate signal LG outputted from the drive circuit 7 goes to the xe2x80x9cHxe2x80x9d level so that the low-side switching element is driven to turn on. Further, when the low-side input signal LS falls to the xe2x80x9cLxe2x80x9d level (timing t4), the low-side gate signal LG outputted from the drive circuit 7 goes to the xe2x80x9cLxe2x80x9d level so that driving of the low-side switching element 8 is stopped (off).
However, in the gate driver having a structure as described above, the high-side input signal HS must be once converted into an ON pulse Pon and an OFF pulse Poff and must be converted again into ON/OFF signals of the high-side switching element, on the ground that signals must be transmitted from circuits of the low-side system to circuits of the high-side system having a different reference potential as that of the circuits of the low-side system. Therefore, an erroneous ON pulse is generated under influences from shifts of noise and outputs (e.g., voltage changes caused mainly between reference potentials). Even when OFF status of the high-side switching element 6 is instructed by the high-side input signal HS, there may be a possibility to turn on erroneously (corresponding to the operation at the timing t5). If the low-side switching element 8 is turned on (operation at the timing t6) in a state that the high-side switching element is suddenly turned on erroneously, a penetrating current flows between the power supply VC and the ground point GND, so that there may be a forced stop due to operation of an excessive current protect circuit (not shown) and breakdown of the switching elements 6 and 8 in the worst case.
Therefore, the present invention has an object of providing a gate driver capable of preventing breakdown of output elements (switching elements).
The present invention also has another object of providing a gate driver and a power converter capable of eliminating abnormal operation even in case where output elements (switching elements) hold erroneously their on status.
The present invention has further another object of providing a gate driver capable of preventing high-side and low-side switching elements from simultaneously turning on even if the high-side switching element is erroneously rendered on when a high-side input signal instructs the high-side switching element to be off.
The present invention has further another object of providing a gate driver capable of preventing forced stop due to operation of an excessive current protect circuit which is caused by a penetrating current flowing between a power supply and a ground point.
The present invention has further another object of providing a gate driver capable of saving space and reducing costs.
The above-described objects of the present invention are achieved by a gate driver comprising: an edge detection circuit for detecting leading and trailing edges of a control input signal; an ON pulse generation circuit for generating an ON pulse in response to the leading or trailing edge of the control input signal, which is detected by the edge detection circuit; a first OFF pulse generation circuit for generating a first OFF pulse in response to the leading or trailing edge of the control input signal, which is detected by the edge detection circuit; a status hold circuit for driving an output element in response to the ON pulse outputted from the ON pulse generation circuit and for holding driving status of the output element until the first OFF pulse is outputted from the first OFF pulse generation circuit; and a second OFF pulse generation circuit for generating a second OFF pulse in response to a protect operation signal and for supplying the second OFF pulse to the status hold circuit, thereby to stop driving of the output element when protect operation is instructed by the protect operation signal.
According to the structure described above, the output element can be turned off by outputting a second OFF pulse from the second OFF pulse generation circuit, even if an output element is turned on due any reason when input of the control input signal is stopped. Therefore, it is possible to eliminate abnormal operation when the output element erroneously holds on status, and it is thus possible to prevent breakdown of the output element.
Also, the objects of the present invention are achieved by a gate driver comprising: an edge detection circuit supplied with a control input signal and a protect operation signal, for detecting leading and trailing edges of the control input signal, the edge detection circuit being let stop operating when protect operation is instructed by the protect operation signal; an ON pulse generation circuit for generating an ON pulse in response to the leading or trailing edge of the control input signal, which is detected by the edge detection circuit; a first OFF pulse generation circuit for generating a first OFF pulse in response to the leading or trailing edge of the control input signal, which is detected by the edge detection circuit; a status hold circuit for driving an output element and for holding driving status of the output element until the first OFF pulse is outputted from the first OFF pulse generation circuit; and a second OFF pulse generation circuit for generating a second OFF pulse in response to the control input signal and the protect operation signal and for providing the second OFF pulse to the status hold circuit, wherein when turn-off of the output element is instructed by the control input signal and protect operation is instructed by the protect operation signal, the second OFF pulse is outputted to stop driving of the output element.
According to the structure as described above, turn-off of an output element can be instructed by the control input signal even if the output element is turned on due to any reason when input of the control input signal is stopped, and the output element can be turned off by outputting the second OFF pulse from the second OFF pulse generation circuit when protect operation is instructed by the protect operation signal. Therefore, even if the output element erroneously holds the on status of the output element, abnormal operation can be eliminated so that breakdown of the output element can be prevented. Besides, even if the OFF pulse generation circuit erroneously operates due to noise or the like, the on status of the output element can be held when on of the output element is instructed by the control input signal. As a result, immunity can be improved.
Further, the objects of the present invention are achieved by a gate driver comprising: an abnormality detection circuit for detecting abnormal status; a protect operation signal generation circuit for generating a protect operation signal when an abnormality is detected by the abnormality detection circuit; a first determination circuit inputted with a control input signal of a high side, a control input signal of a low side, and the protect operation signal, for determining whether the control input signal of the high-side can be transmitted or not depending on status of the control input signal of the low side and the protect operation signal; a second determination circuit inputted with a control input signal of a high side, a control input signal of a low side, and the protect operation signal, for determining whether the control input signal of the low side can be transmitted or not depending on status of the control input signal of the high side and the protect operation signal, and to drive the low-side output element; a trigger signal generation circuit inputted with the protect operation signal, for generating a trigger signal for generating a high-side OFF pulse in synchronization with generation of the protect operation signal; a third determination circuit supplied with the trigger signal outputted from the trigger signal generation circuit and an output signal from the first determination circuit, for determining whether the trigger signal can be transmitted or not depending on status of the control input signal of the high side; an OFF pulse generation circuit supplied with the output signal from the first determination circuit and an output signal from the third determination circuits, for detecting falling of the control input signal of the high side and falling of the trigger signal and for generating an OFF pulse; an ON pulse generation circuit supplied with the output signal of the first determination circuit, for detecting rising of the control input signal of the high side, and for generating an ON pulse; and a status hold circuit for driving a high-side output element in response to the ON pulse outputted from the ON pulse generation circuit, and for holding driving status of the high-side output element until the OFF pulse is outputted from the OFF pulse generation circuit.
In this kind of structure, the side of the high-side output element which may cause abnormal operation can be steadily turned off when an abnormality is detected by the abnormality detection circuit in case where high-side and low-side output elements are used. Thus, abnormal operation is eliminated and breakdown of the output elements can be effectively prevented.
Further, the objects of the present invention are achieved by a power converter constructed by integrating a gate driver and an output element driven by the gate driver, in one-chip, the gate driver comprising: an edge detection circuit for detecting output element are formed in one-chip, so that space saving and cost reduction of the power converter can be achieved.
Also, the objects of the present invention are achieved by a power converter constructed by integrating a gate driver and high-side and low-side output elements driven by the gate driver, in one-chip, the gate driver comprising: an abnormality detection circuit for detecting abnormal status; a protect operation signal generation circuit for generating a protect operation signal when an abnormality is detected by the abnormality detection circuit; a first determination circuit inputted with a control input signal of a high side, a control input signal of a low side, and the protect operation signal, for determining whether the control input signal of the high-side can be transmitted or not depending on status of the control input signal of the low side and the protect operation signal; a second determination circuit inputted with a control input signal of a high side, a control input signal of a low side, and the protect operation signal, for determining whether the control input signal of the low side can be transmitted or not depending on status of the control input signal of the high side and the protect operation signal, and to drive the low-side output element; a trigger signal generation circuit inputted with the protect operation leading and trailing edges of a control input signal; an ON pulse generation circuit for generating an ON pulse in response to the leading or trailing edge of the control input signal, which is detected by the edge detection circuit; a first OFF pulse generation circuit for generating a first OFF pulse in response to the leading or trailing edge of the control input signal, which is detected by the edge detection circuit; a status hold circuit for driving the output element in response to the ON pulse outputted from the ON pulse generation circuit and for holding driving status of the output element until the first OFF pulse is outputted from the first OFF pulse generation circuit; and a second OFF pulse generation circuit for generating a second OFF pulse in response to a protect operation signal and for supplying the second OFF pulse to the status hold circuit, thereby to stop driving of the output element.
In the structure as described above, the output element can be turned off by outputting a second OFF pulse from the second OFF pulse generation circuit, even if an output element is turned on due any reason when input of the control input signal is stopped. Therefore, it is possible to eliminate abnormal operation when the output element erroneously holds on status, and it is thus possible to prevent breakdown of the output element. Besides, the gate driver and the signal, for generating a trigger signal for generating a high-side OFF pulse in synchronization with generation of the protect operation signal; a third determination circuit supplied with the trigger signal outputted from the trigger signal generation circuit and an output signal from the first determination circuit, for determining whether the trigger signal can be transmitted or not depending on status of the control input signal of the high side; an OFF pulse generation circuit supplied with the output signal from the first determination circuit and an output signal from the third determination circuits, for detecting falling of the control input signal of the high side and falling of the trigger signal and for generating an OFF pulse; an ON pulse generation circuit supplied with the output signal of the first determination circuit, for detecting rising of the control input signal of the high side, and for generating an ON pulse; and a status hold circuit for driving a high-side output element in response to the ON pulse outputted from the ON pulse generation circuit, and for holding driving status of the high-side output element until the OFF pulse is outputted from the OFF pulse generation circuit.
In this kind of structure, the side of the high-side output element which may cause abnormal operation can be steadily turned off when an abnormality is detected by the abnormality detection circuit in case where high-side and low-side output elements are used. Thus, abnormal operation is eliminated and breakdown of the output elements can be effectively prevented. Besides, the gate driver and the output elements are formed in one-chip, so that space saving and cost reduction can be achieved.
The above-described objects of the present invention are achieved by a gate driver for controlling high-side and low-side switching elements constructed in a push/pull structure, comprising a high-side gate driver circuit for driving the high-side switching element in response to a high-side input signal, and a low-side gate driver circuit for driving the low-side switching element, the high-side gate driver circuit including: a first edge detection circuit for detecting leading and trailing edges of the high-side input signal for driving the high-side switching element; a second edge detection circuit for detecting leading and trailing edges of the low-side input signal for driving the low-side switching element; an ON pulse generation circuit for generating an ON pulse, based on a detection output of the first edge detection circuit; an OFF pulse generation circuit for generating an OFF pulse, based on detection outputs of the first and second edge detection circuits; a latch circuit supplied with each of the ON pulse outputted from the ON pulse generation circuit and the OFF pulse outputted from the OFF pulse generation circuit, for holding ON/OFF information of the high-side switching element instructed by the high-side input signal; and a drive circuit for outputting a high-side gate signal for controlling the high-side switching element in accordance with the ON/OFF information held by the latch circuit, and when driving of the low-side switching element is instructed by the low-side input signal, the OFF pulse is generated from the OFF pulse generation circuit thereby to forcedly turn off the high-side switching element.
According to the structure as described above, the OFF pulse is generated from the OFF pulse generation circuit so that the high-side switching element is forcedly turned off when the low-side switching element is turned on even if the high-side switching element is suddenly tuned on erroneously due to influences of noise or a change of an output potential in a state where turn-off of the high-side switching element is instructed by a high-side input signal. It is therefore possible to prevent the high-side and low-side switching elements from being on simultaneously. Accordingly, it is possible to prevent forced stop and breakdown of switching elements due to operation of the excessive current protect circuit which is caused by a penetrating current flowing between the power supply and a ground point.
Also, the objects of the present invention are achieved by a power converter constructed by integrating a high-side and low-side switching elements having a push/pull structure, a high-side gate driver circuit for driving the high-side switching element in response to a high-side input signal, and a low-side gate driver circuit for driving the low-side switching element in response to a low-side input signal, in one-chip, the high-side gate driver circuit including: a first edge detection circuit for detecting leading and trailing edges of the high-side input signal for driving the high-side switching element; a second edge detection circuit for detecting leading and trailing edges of the low-side input signal for driving the low-side switching element; an ON pulse generation circuit for generating an ON pulse, based on a detection output of the first edge detection circuit; an OFF pulse generation circuit for generating an OFF pulse, based on detection outputs of the first and second edge detection circuits; a latch circuit supplied with each of the ON pulse outputted from the ON pulse generation circuit and the OFF pulse outputted from the OFF pulse generation circuit, for holding ON/OFF information of the high-side switching element instructed by the high-side input signal; and a drive circuit for outputting a high-side gate signal for controlling the high-side switching element in accordance with the ON/OFF information held by the latch circuit, wherein when driving of the low-side switching element is instructed by the low-side input signal, the OFF pulse is generated from the OFF pulse generation circuit thereby to forcedly turn off the high-side switching element.
According to the structure as described above, the OFF pulse is generated from the OFF pulse generation circuit so that the high-side switching element is forcedly turned off when the low-side switching element is turned on even if the high-side switching element is suddenly tuned on erroneously due to influences of noise or a change of an output potential in a state where turn-off of the high-side switching element is instructed by a high-side input signal. It is therefore possible to prevent the high-side and low-side switching elements from being on simultaneously. Accordingly, it is possible to prevent forced stop and breakdown of switching elements due to operation of the excessive current protect circuit which is caused by a penetrating current flowing between the power supply and a ground point. Besides, the gate driver and the output elements are formed in one-chip, so that space saving and cost reduction can be achieved.
Also, the objects of the present invention are achieved by a gate driver for controlling the high-side and low-side switching elements having a push/pull structure, comprising a high-side gate driver circuit for driving the high-side switching element in response to a high-side input signal, and a low-side gate driver circuit for driving the low-side switching element in response to a low-side input signal, the high-side gate driver circuit including: an edge detection circuit for detecting leading and trailing edges of the high-side input signal for driving the high-side switching element; an input terminal externally inputted with a high-side forced OFF signal for forcedly turning off the high-side switching element; an ON pulse generation circuit for generating an ON pulse, based on a detection output of the edge detection circuit; an OFF pulse generation circuit for generating an OFF pulse, based on the detection output of the edge detection circuit and the high-side forced OFF signal inputted through the input terminal; a latch circuit supplied with each of the ON pulse outputted from the ON pulse generation circuit and the OFF pulse outputted from the OFF pulse generation circuit, for holding ON/OFF information of the high-side switching element instructed by the high-side input signal; and a drive circuit for outputting a high-side gate signal for controlling the high-side switching element in accordance with the ON/OFF information held by the latch circuit, wherein when the input terminal is inputted with the high-side forced OFF signal, the high-side switching element is forcedly turned off.
According to the structure described above, the high-side switching element is forcedly turned off by a timing signal generated a high-side forced OFF signal inputted from the outside, e.g., a timing signal generated by an external control circuit (such as a micro-computer or the like). Therefore, the high-side switching element is forcedly turned off at an arbitrary timing at which erroneous turning-on easily occurs. While reducing the current consumption to the minimum, the high-side and low-side switching elements can be prevented from being on simultaneously. As a result, it is possible to prevent forced stop and breakdown of switching elements due to operation of the excessive current protect circuit which is caused by a penetrating current flowing between the power supply and a ground point.
Further, the objects of the present invention are achieved by a power converter constructed by integrating high-side and low-side switching elements having a push/pull structure, a high-side gate driver circuit for driving the high-side switching element in response to a high-side input signal, and a low-side gate driver circuit for driving the low-side switching element in response to a low-side input signal, in one-chip, the high-side gate driver circuit including: an edge detection circuit for detecting leading and trailing edges of the high-side input signal for driving the high-side switching element; an input terminal externally inputted with a high-side forced OFF signal for forcedly turning off the high-side switching element; an ON pulse generation circuit for generating an ON pulse, based on a detection output of the edge detection circuit; an OFF pulse generation circuit for generating an OFF pulse, based on the detection output of the edge detection circuit and the high-side forced OFF signal inputted through the input terminal; a latch circuit supplied with each of the ON pulse outputted from the ON pulse generation circuit and the OFF pulse outputted from the OFF pulse generation circuit, for holding ON/OFF information of the high-side switching element instructed by the high-side input signal; and a drive circuit for outputting a high-side gate signal for controlling the high-side switching element in accordance with the ON/OFF information held by the latch circuit, wherein when the input terminal is inputted with the high-side forced OFF signal, the high-side switching element is forcedly turned off.
According to the structure described above, the high-side switching element is forcedly turned off by a timing signal generated a high-side forced OFF signal inputted from the outside, e.g., a timing signal generated by an external control circuit (such as a micro-computer or the like). Therefore, the high-side switching element is forcedly turned off at an arbitrary timing at which erroneous turning-on easily occurs. While reducing the current consumption to the minimum, the high-side and low-side switching elements can be prevented from being on simultaneously. As a result, it is possible to prevent forced stop and breakdown of switching elements due to operation of the excessive current protect circuit which is caused by a penetrating current flowing between the power supply and a ground point. Besides, the gate driver and the output elements are formed in one-chip, so that space saving and cost reduction can be achieved.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.